We have already used make to build single file programs. It was really designed to help build large multi-file programs. Its use will be described here.
Make knows about `dependencies' in program building. For example;
make is usually used with a configuration file called Makefile which describes the structure of the program. This includes the name of the runnable file, and the object files to be linked to create it. Here is a sample Makefile for our current example
# Sample Makefile for prog # # prog is built from prog.c func1.c func2.c # # Object files (Ending in .o, # these are compiled from .c files by make) OBJS = prog.o func1.o func2.o # Prog is generated from the object files prog: $(OBJS) $(CC) $(CFLAGS) -o prog $(OBJS) # ^^^ This space must be a TAB. # Above line is an instruction to link object files
This looks cluttered, but ignore the comments (lines starting with #) andthere are just 3 lines.
When make is run, Makefile is searched for a list of dependencies. The compiler is involved to create .o files where needed. The link statement is then used to create the runnable file.
make re-builds the whole program with a minimum of re-compilation, and ensures that all parts of the program are up to date. It has many other features, some of which are very complicated.
For a full description of all of these features, look at the manual page for make by typing
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